Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching
نویسندگان
چکیده
To support FPGA synthesis in the OAGear package, we have implemented the following new components: (i) a cut-based technology mapper for LUT-based FPGA with delay/area optimization options, (ii) an efficient SAT-based Boolean matcher (SAT-BM) for both single-output and multipleoutput Boolean functions, and (iii) an area-aware resynthesis algorithm using this SAT-BM. The SAT-BM incorporates the recent improvements presented in [1], which shows over 200x speedup compared to the original SAT-BM algorithm [2]. The resynthesis considers both single-output and multiple-output logic blocks [3] and reduces the number of LUTs by up to 1.4%, compared to Berkeley ABC mapper.
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